1. Field of Invention
The present invention relates to an electrostatic discharge (ESD) device. More particularly, the present invention relates to an ESD device that is used with a high-voltage input pad.
2. Description of Related Art
Electrostatic discharge (ESD) is a phenomenon where electrostatic charges migrate from a non-conductive surface via conductive material. Since an electrostatic voltage is usually quite high, the ESD phenomenon can easily damage the substrate and other components of an integrated circuit. For example, an electrostatic voltage from hundreds to thousands of volts can be created on a human body walking on a carpet under a higher relative humidity, while more than 10,000 volts can be created under a lower relative humidity. Also, an electrostatic voltage from hundreds to thousands of volts can be created in machines for packaging or testing integrated circuits. Therefore, when a human body or a machine carrying electrostatic charges contacts with a chip, a large transient ESD current is generated damaging or destroying the integrated circuits on the chip.
To protect the integrated circuits from being damaged by ESD, ESD devices capable of conducting an ESD current to ground are incorporated into the integrated circuits. The ESD devices used in electrically programmable non-volatile memory devices, most of which use a high voltage, such as 12.5 V, to generate hot electrons for programming, must be specially designed to fit with high voltages. One type of ESD protection circuit frequently used for protecting such memory devices is the two-stage circuit described below.
FIG. 1 illustrates a programmable memory apparatus and a two-stage protection circuit thereof in the prior art.
Referring to FIG. 1, a programmable memory device 101 is disposed on a substrate 100 with a high-voltage input pad 102 electrically connected thereto for providing a high voltage in a programming operation. A two-stage protection circuit 108 is coupled between the memory device 101 and the high-voltage input pad 102 to protect the memory device 101 from being damaged by ESD.
The two-stage protection circuit 108 comprises a primary device 104, a secondary device 106 and a resistor 110 coupled between them. As an ESD event happens to the programmable memory apparatus via the high-voltage input pad 102, the first device 104 serves to shunt most ESD current. The second device 106 therefore can provide the memory device 101 with a clamping voltage within a safe range.
In the prior art, a gate-grounded NMOS (GGNMOS) transistor is used as the second device 106 in the two-stage protection circuit 108. The second device 106 consisting of a single GGNMOS is illustrated in FIG. 2, wherein the gate and the source of the GGNMOS are both grounded.
However, such a secondary device has a disadvantage that its breakdown voltage is lower than the programming voltage of a non-volatile memory device that uses hot electrons for programming. Therefore, the ESD protection mechanism (breakdown mechanism) of the secondary device is triggered on programming, and a severe leakage is caused interfering with the programming operation. For example, an ordinary gate bias for hot-electron programming is about 10 V, while the breakdown voltage of a GGNMOS transistor is merely 9.5 V. Since the programming voltage of 10 V immediately causes a breakdown of the GGNMOS transistor, the programming operation cannot be well done.
Accordingly, this invention provides an ESD device used with a high-voltage input pad. The ESD device serves as a secondary device in a two-stage protection circuit, and provides a higher breakdown voltage as compared with the conventional secondary device.
The ESD device used with a high-voltage input pad of this invention comprises a substrate, a first NMOS transistor and a second NMOS transistor. The first NMOS transistor is disposed on the substrate and comprises a first gate, a first source and a first drain, and is preferably one without lightly doped drain regions, i.e., a non-LDD NMOS transistor. In this invention, the first gate is coupled to a positive bias Vg1, such as 3.3 V, and the first drain is coupled to the high-voltage input pad that provides a voltage higher than 10 V during a programming operation. The second NMOS transistor is also disposed on the substrate and comprises a second gate, a second drain and a second source, wherein the second gate and the second source are both grounded, and the second drain is electrically connected with the first source of the first NMOS transistor. With the first NMOS transistor, the breakdown voltage of the secondary device can be raised to 12.7 V.
This invention also provides a programmable memory apparatus, which comprises a substrate, a memory device, a high-voltage input pad and a two-stage protection circuit. The memory device and the high-voltage input pad are disposed on the substrate, and are electrically connected with each other. The two-stage protection circuit is disposed on the substrate and coupled between the memory device and the high-voltage input pad, and comprises a primary device, a secondary device and a resistor coupled between them. The secondary device comprises a substrate, a first NMOS transistor and a second NMOS transistor. The first NMOS transistor Is disposed on the substrate and comprises a first gate, a first drain and a first source, and is preferably one without lightly doped drain regions, i.e., a non-LDD NMOS transistor. In this invention, the first gate is coupled to a bias Vg1, such as 3.3 V, and the first drain is coupled to the high-voltage input pad that provides an input voltage higher than 10 V during a programming operation. The second NMOS transistor is also disposed on the substrate and comprises a second gate, a second drain and a second source, wherein the second gate and the second source are both grounded, and the second drain is electrically connected with the first source of the first NMOS transistor. With the first NMOS transistor, the breakdown voltage of the secondary device can be raised to 12.7 V. Therefore, when the memory device is being programmed with a high voltage up to 10 V, the ESD protection mechanism of the secondary device is not triggered, and the programming operation can be implemented successfully.
By using the ESD device of this invention as the secondary device in a two-stage protection circuit used with a high-voltage input pad, the breakdown voltage of the secondary device can be raised effectively. Therefore, a leakage of the secondary device can be effectively prevented.
Accordingly, in the programmable memory apparatus of this invention, the ESD device of the invention does not only protect the memory device from being damaged by ESD, but also fits with the high voltages required in a programming operation.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.